Applications are invited for ‘Junior Research Fellow/Senior Research Fellow’ for DST Project in School of Electronics Engineering, VIT University, Chennai.
Project Title : Development of a SPICE-Compatible Model for Single Event Transients for Circuit Simulations and its Application in SET-Tolerant DLL Design.
Sponsoring Agency: SERB, DST, New Delhi.
Number of Positions: One
Duration: 3 years
Designation & Qualifications :
Junior Research Fellow :
First Class M.E/M.Tech in VLSI Design/Microelectronics (or closely associated streams/branches). Preference will be given to candidates with GATE score.
Salary per month - Rs. 25,000/- pm + 10% HRA
Senior Research Fellow :
Qualification prescribed for JRF with two years of research experience in Nanoelectronics/VLSI Design.
Salary per month - Rs. 28,000/- pm + 10% HRA
Last date for receipt of Application: 21st Nov. 2016......
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