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Designation: Physical Designer
Years of Exp : 3-12 years
Location : Bangalore
ICC, block level and some top level experience.
Design planning, partition, full chip level floorplan, bump placement, bump routing, power routing, block level floorplan, power plan, place and route, CTS, STA, physical verification, DRC, LVS, IR-EM analysis, debugging gds level issues, giving technical guidance to junior engineers in block/full chip level activities.
Working experience in 14nm or lower geometry is advantage.
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Preferably who can join early would be considerable
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