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Experience: 3 to 12 yrs
Qualification: BE/BTech, ME/MTech (VLSI Domain)
Role and responsibility:
• Ability to execute block level and SOC level P&R and Timing closure activities.
• Will be responsible for owning up IR/EM/ESD simulations for the various CPU.
• Perform RTL2GDS or Netlist2GDS on blocks and/or fullchip for SoC designs executed by Foundry.
• This design group is designing some of the critical SoCs using Intel foundry design kits.
• The key responsibility is to independently own and converge partitions and sections on 14nm and below processes and execution in converging their blocks for implementation and timing
• Implementation of multimillion gate SoC designs in cutting edge process technologies (28nm,16nm,14nm & below).
• Strong Hands-on expertise on any of the aspects of physical design including Synthesis, Floor Planning, Power Plan, Integrated Package and Floorplan design, Place and Route, Clock Planning and Clock Tree Synthesis, complex analog IP integration, Parasitic Extraction, Timing Closure, Power / IR Drop (Static and Dynamic), Signal Integrity Analysis, Physical Verification (DRC, ERC, LVS), DFM and DFY and Tapeout.
• Expertise in analyzing and converging on crosstalk delay, noise glitch, and electrical rules in deep-sub micron processes required. Understanding of process variation effects, and experience in variations analysis/modeling techniques and convergence mechanism would be a plus.
• Expertise in Synopsys IC compiler, Magma or Cadence SOC encounter physical design tools.
• Skill and experience in scripting using Tcl or Perl is highly desirable
If interested please share your resumes to Ranjitha.firstname.lastname@example.org
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